We describe a simulator that is a useful supporting tool in all activities involving computer architecture teaching. The system, developed using an object-oriented approach, integrates in a single tool different architecture models, such as CISC and RISC architecture types, and different computer levels, such as microprogramming and instruction set levels. The system allows the user to define the computer architecture at the instruction set level and then to switch automatically to the lower level of the corresponding microarchitecture. The simulation process consists of a loop, in which two strictly correlated phases are executed: the definition phase, in which the user defines the architecture through a choice of hardware components, and a test phase, in which the user tests the designed architecture in order to verify the result of the design activity of the previous phase. Once the processor design has been completed through this simulation process, the tool allows the user to save and use a stand-alone simulator of the target computer architecture. The definition and simulation activities of the computer architecture are supported by a graphical user interface for an effective, easy-to-use teaching environment.

An Object Oriented Tool to Simulate Multi-Level Computer Architectures

PIZZUTILO, Sebastiano;TANGORRA, Filippo
2003-01-01

Abstract

We describe a simulator that is a useful supporting tool in all activities involving computer architecture teaching. The system, developed using an object-oriented approach, integrates in a single tool different architecture models, such as CISC and RISC architecture types, and different computer levels, such as microprogramming and instruction set levels. The system allows the user to define the computer architecture at the instruction set level and then to switch automatically to the lower level of the corresponding microarchitecture. The simulation process consists of a loop, in which two strictly correlated phases are executed: the definition phase, in which the user defines the architecture through a choice of hardware components, and a test phase, in which the user tests the designed architecture in order to verify the result of the design activity of the previous phase. Once the processor design has been completed through this simulation process, the tool allows the user to save and use a stand-alone simulator of the target computer architecture. The definition and simulation activities of the computer architecture are supported by a graphical user interface for an effective, easy-to-use teaching environment.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11586/2267
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